Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/147509
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dc.contributor.authorPiyasena, Duvinduen_US
dc.contributor.authorWickramasinghe, Rukshanen_US
dc.contributor.authorPaul, Debdeepen_US
dc.contributor.authorLam, Siew-Keien_US
dc.contributor.authorWu, Meiqingen_US
dc.date.accessioned2021-04-19T03:27:20Z-
dc.date.available2021-04-19T03:27:20Z-
dc.date.issued2019-
dc.identifier.citationPiyasena, D., Wickramasinghe, R., Paul, D., Lam, S. & Wu, M. (2019). Lowering dynamic power of a stream-based CNN hardware accelerator. 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP), 1-6. https://dx.doi.org/10.1109/MMSP.2019.8901777en_US
dc.identifier.isbn9781728118178-
dc.identifier.urihttps://hdl.handle.net/10356/147509-
dc.description.abstractCustom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy.en_US
dc.description.sponsorshipNational Research Foundation (NRF)en_US
dc.language.isoenen_US
dc.relationTUM CREATEen_US
dc.rights© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/MMSP.2019.8901777en_US
dc.subjectEngineering::Computer science and engineering::Hardware::Register-transfer-level implementationen_US
dc.subjectEngineering::Computer science and engineering::Computing methodologies::Image processing and computer visionen_US
dc.titleLowering dynamic power of a stream-based CNN hardware acceleratoren_US
dc.typeConference Paperen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.contributor.conference2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP)en_US
dc.contributor.researchHardware & Embedded Systems Lab (HESL)en_US
dc.identifier.doi10.1109/MMSP.2019.8901777-
dc.description.versionAccepted versionen_US
dc.identifier.scopus2-s2.0-85075739729-
dc.identifier.spage1en_US
dc.identifier.epage6en_US
dc.subject.keywordsFPGAen_US
dc.subject.keywordsConvolutional Neural Networksen_US
dc.citation.conferencelocationKuala Lumpur, Malaysiaen_US
dc.description.acknowledgementThis research project is funded by the National Research Foundation Singapore under its Campus for Research Excellence and Technological Enterprise (CREATE) programme with the Technical University of Munich at TUMCREATE.en_US
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