Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate

Abstract

The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of < 10% on a 300-mm wafer. Two trap types designed with radio-frequency (RF) linewidth of 80 and $40~\mu \text{m}$ are evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB and $Q$ factor increment of 2 and 6 for the corresponding trap types.