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|Title:||Fast prototyping of neural network on hardware accelerator||Authors:||Agus, Hans Kevin||Keywords:||Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence
|Issue Date:||2021||Publisher:||Nanyang Technological University||Source:||Agus, H. K. (2021). Fast prototyping of neural network on hardware accelerator. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149144||Abstract:||This project aims to implement Convolutional Neural Network (CNN) and Spiking Neural Network (SNN) in FPGA using Vivado High Level Synthesis (HLS), followed by analyzing and comparing the performance based on the speed, accuracy, utilization, and power consumption. The goal is to have a neural network running on FPGA with low latency, low resources, and low power so that the neural network can be implemented in low power and low resource environment to do real-time recognition tasks. This would be done by using the optimizations available in Vivado HLS. Furthermore, two learning rules of Spiking Neural Network, namely Spike Timing Dependent Plasticity (STDP) and Deep Belief Network (DBN) with Restricted Boltzmann Machine (RBM), were also simulated to obtain the trained weights before implementing the SNN on FPGA. The FPGA-implemented CNN in this project achieved 97.39% accuracy, which is equal to software-based implementation with the same network configuration. Furthermore, the latency of the network was 0.687 ms, which is comparable to the software-based implementation running on CPU. The SNNs were also implemented on FPGA with two different types of operation, which are time-step based and event-driven. The time-step based SNN by utilizing Siegert neurons achieved 92.19% accuracy with 20.35 ms latency, while the event-driven SNN achieved 86.8% accuracy with 3.72 s latency. Furthermore, this project had shown that the event-driven operation was better for low resources and low power, while the time-step operation was better for latency and accuracy.||URI:||https://hdl.handle.net/10356/149144||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
Updated on Jun 27, 2022
Updated on Jun 27, 2022
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