Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/149182
Title: FPGA implementation of spiking convolutional neural networks for voice keyword recognition
Authors: Ng, Wei Soon
Keywords: Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence
Engineering::Electrical and electronic engineering
Issue Date: 2021
Publisher: Nanyang Technological University
Source: Ng, W. S. (2021). FPGA implementation of spiking convolutional neural networks for voice keyword recognition. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149182
Project: B2063-201
Abstract: The spiking convolutional neural network (SCNN) is a hybrid model of both the spiking neural network (SNN) and convolutional neural network (CNN). It is known to be power efficient and accurate. Although SCNN has shown promising accuracy for voice keyword recognition in software environment, its computation time remains the biggest challenge of the model. To improve the computational speed of SCNN, a highly efficient Field-Programmable Gate Array (FPGA)-based SCNN hardware architecture for voice keyword recognition is proposed in this project. The design methodology engages the parallelism and flexibility of FPGA to achieve high speed computation. The proposed architecture is fully pipelined to maximize the efficiency of the system. Furthermore, the spiking model used in this work is the Izhkevich spiking model [1] which is of much less complexity and yet able to achieve competitive accuracy when compared to the Hodgkin-Huxley spiking model [2]. The proposed SCNN model achieves an accuracy of 89% with zero accuracy loss upon mapping from the software environment to the hardware environment. Besides, through retraining and fixed-point quantization techniques, the memory consumption of weights and other parameters stored on FPGA is reduced by 8 times without compromising the accuracy. The proposed design flow for implementing the SCNN model serves as a good reference for future design, to help reduce the development time of SCNN model on FPGA.
URI: https://hdl.handle.net/10356/149182
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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