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dc.contributor.authorLiu, Yanen_US
dc.contributor.authorDing, Luen_US
dc.contributor.authorCao, Yuen_US
dc.contributor.authorWan, Dongyangen_US
dc.contributor.authorYuan, Guanghuien_US
dc.contributor.authorHuang, Baohuen_US
dc.contributor.authorThean, Aaron Voon-Yewen_US
dc.contributor.authorMei, Tingen_US
dc.contributor.authorVenkatesan, Thirumalaien_US
dc.contributor.authorNijhuis, Christian A.en_US
dc.contributor.authorChua, Soo-Jinen_US
dc.identifier.citationLiu, Y., Ding, L., Cao, Y., Wan, D., Yuan, G., Huang, B., Thean, A. V., Mei, T., Venkatesan, T., Nijhuis, C. A. & Chua, S. (2020). The design of CMOS-compatible plasmonic waveguides for intra-chip communication. IEEE Photonics Journal, 12(5), 4800810-.
dc.description.abstractA CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO₂ with much smaller and hence denser interconnects,are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of∼19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ∼0.18 ps and 0.19 ps,energy dissipation per computing bit of ∼2.5×10⁻³ fJ/bit and 3.8×10⁻³ fJ/bit, and 25% crosstalk coupling length of 155μm and 125μm. These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.en_US
dc.description.sponsorshipNational Research Foundation (NRF)en_US
dc.relation.ispartofIEEE Photonics Journalen_US
dc.rights© 2020 The Author(s). This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see
dc.titleThe design of CMOS-compatible plasmonic waveguides for intra-chip communicationen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Physical and Mathematical Sciencesen_US
dc.contributor.researchCentre for Disruptive Photonic Technologies (CDPT)en_US
dc.contributor.researchThe Photonics Instituteen_US
dc.description.versionPublished versionen_US
dc.subject.keywordsCMOS-compatible Plasmonic Waveguideen_US
dc.subject.keywordsLong-range SPPen_US
dc.description.acknowledgementThis research was supported by National Research Foundation Singapore project of Integration of Electrically Driven Plasmonic Components in High Speed (NRF2016_CRP001_111).en_US
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