Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/149436
Title: 16-bit high speed CMOS multiplier IC design
Authors: He, Pengfei
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2021
Publisher: Nanyang Technological University
Source: He, P. (2021). 16-bit high speed CMOS multiplier IC design. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149436
Abstract: With the continuous development of the semiconductor industry, the scale of digital integrated circuits is getting bigger and bigger, and the degree of integration is getting higher and higher. In modern applications, speed has become an indicator that people pay much attention to. In a digital system, the overall performance is greatly affected by the calculation speed of the multiplier, because the arithmetic logic unit (ALU) is one of the most time-consuming parts of the digital system. In this dissertation, a 16-bit high-speed multiplier was designed using Verilog hardware description language and compared with several commonly used multipliers. First, this dissertation introduces the basic process of digital circuit design and the basic knowledge of digital circuits, and then introduces the Booth algorithm and Wallace tree technique on the basis of reviewing the literature. Then a 16-bit multiplier was designed based on the modified Booth 2 algorithm and Wallace tree technique, and the RTL code was implemented using Verilog HDL. In order to highlight the excellent performance of the multiplier in terms of operating speed, this dissertation has designed several common multipliers and implemented them in Verilog. Last but not least, this article uses VCS to simulate the above-mentioned multipliers to verify the correctness of their functions, and after using Design Compiler (DC) to synthesize, compares their operating speeds through the delay information of the post-simulation. In the end, it has been successfully simulated that the delay of the multiplier based on the modified Booth 2 algorithm and Wallace tree technique is about 23263ps (or 23.263ns).
URI: https://hdl.handle.net/10356/149436
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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