Digital class-D amplifier

Abstract

This report describes the design of a noise-shaping pre-processing stage for a 16-bit digital Class-D audio amplifier based on Sigma Delta Modulation (SDM). The development of the project is divided into two phases: design of Simulink model and implementation on FPGA. The input signal of a typical Digital Class-D amplifier is a 16-bit PCM (Pulse Code Modulation) signal with a sampling frequency of 44.1 kHz. However, due to the limitation of the clock frequency of the digital PWM (Pulse Wave Modulator), it can only process digital signals up to 10 bit resolution, which suggests the noise floor could rise to -60 dB. To enhance the quality of the audio signal, there is a need to reduce the noise floor to -80 dB by employing SDM. An oversampled SDM can reduce the in-band noise by shaping the noise to high frequency band. The Signal to Noise Ratio (SNR) performance is related to both the order of the modulator and the oversampling ratio (OSR). After the calculation and pre-simulation are finished, the second order SDM employing CRFB (Cascaded Resonator Feed Back) topology with an OSR of 128 is selected for this design purpose. The design and simulation of a Sigma Delta Modulator is conducted using Simulink. An additional toolbox available online is also used to perform the calculation, analysis and simulation. A Xilinx FPGA chip is chosen for the implementation while the VHDL modules are generated by HDL Coder available in MATLAB. The simulation results have shown that this design has fulfilled the 80 dB specifications for the SNR and there is no problems regarding the stability.