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|Title:||Simulation of resistive random-access memory (RRAM) : SPICE modelling of RRAM device||Authors:||Lian, Jie||Keywords:||Engineering::Electrical and electronic engineering::Microelectronics||Issue Date:||2021||Publisher:||Nanyang Technological University||Source:||Lian, J. (2021). Simulation of resistive random-access memory (RRAM) : SPICE modelling of RRAM device. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149587||Abstract:||Memory is an essential component of the electronic device. Today, nearly 30% area of a chip is taken by different types of memory. Recently, non-volatile memory is becoming more and more popular. For example, the so-called solid-state drive (SSD) is based on non-volatile flash memory, which is dominating the memory industry. As the critical dimension (CD) keeps on reducing, it’s hard for us to overcome the bottleneck of photolithography technology to fabricate the smaller device. New structures are introduced to further increase the device density, such as Multilevel cell (MLC), Tri-level cell (TLC), Qual-level cell (QLC), and even 3D structures. But the structure of the flash memory will still restrict further development. A novel nonvolatile memory – Resistive Random-Access Memory (RRAM) has been investigated for a long time. RRAM is considered a promising candidate for next-generation memory due to its non-volatile property, simple structure, high density, low power consumption, fast speed, multi-bit storage, and CMOS process capability. This dissertation will first review some basic concepts about RRAM and operation principles, conduction mechanisms, and typical materials and structures. Then some compact models are introduced, including two famous models from Stanford University and Peking University, respectively. These models are implanted in LTspice with two methods in this dissertation. After that, some simulations are done based on the models. Two models in the LTspice are flexible and good enough for us to do further simulations. Many other details can be added to describe the complicated mechanisms and some variations for future work, which can give us a better simulation result. Besides the one RRAM component simulation, 1T1R memory cell and memory array simulation can be done with LTspice based on the models we created in this dissertation.||URI:||https://hdl.handle.net/10356/149587||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Jan 22, 2022
Updated on Jan 22, 2022
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