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https://hdl.handle.net/10356/149610
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, Jasmine PeiSi | en_US |
dc.date.accessioned | 2021-06-10T05:17:59Z | - |
dc.date.available | 2021-06-10T05:17:59Z | - |
dc.date.issued | 2021 | - |
dc.identifier.citation | Chen, J. P. (2021). Interactive E-learning environment for phase-locked loop in IC. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149610 | en_US |
dc.identifier.uri | https://hdl.handle.net/10356/149610 | - |
dc.description.abstract | In recent years, the advent of information and communication technology (ICT) drives the education system to strive for integrating ICT into the curriculum framework with the intent of undergirding self-directed learning and exploring interests outside traditional classroom settings. This paper examines and analyses the diverse types of schemes rolled out by the Singapore Ministry of Education to optimise education on a personal level by adapting the four types of learning styles – visual, auditory, reading or writing, and kinesthetic. Based on the analysis, this project aims to develop a learning platform for post-secondary and tertiary students. Microsoft Visual Studio makes it possible to build and design a learning platform. In addition, the advanced functionality of the learning platform connects students to the fundamentals of phase-locked loop with ease. This report highlights a few recommendations for future research, including deploying a dashboard where learners can track their progress, creating a public Uniform Resource Locator (URL) with secure tunnels, and implementing a Universal Serial Bus (USB) oscilloscope in the hardware design. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Nanyang Technological University | en_US |
dc.relation | A2028-201 | en_US |
dc.subject | Engineering::Electrical and electronic engineering | en_US |
dc.title | Interactive E-learning environment for phase-locked loop in IC | en_US |
dc.type | Final Year Project (FYP) | en_US |
dc.contributor.supervisor | Boon Chirn Chye | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Bachelor of Engineering (Electrical and Electronic Engineering) | en_US |
dc.contributor.research | VIRTUS, IC Design Centre of Excellence | en_US |
dc.contributor.supervisoremail | ECCBoon@ntu.edu.sg | en_US |
item.grantfulltext | restricted | - |
item.fulltext | With Fulltext | - |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
File | Description | Size | Format | |
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Chen PeiSi Jasmine_Final Report.pdf Restricted Access | 5.44 MB | Adobe PDF | View/Open |
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