Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/149897
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dc.contributor.authorHe, Weiyangen_US
dc.date.accessioned2021-06-10T04:12:59Z-
dc.date.available2021-06-10T04:12:59Z-
dc.date.issued2021-
dc.identifier.citationHe, W. (2021). Breaking the hardware implementation of AES encryption. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149897en_US
dc.identifier.urihttps://hdl.handle.net/10356/149897-
dc.description.abstractAdvanced Encryption Standard (AES) is an extensively used symmetric block cipher algorithm which generates ciphertext based on plaintext and key (128, 192, or 256 bits) inputs. Recover the cipher key through brute-force attempts is unrealistic due to the extremely high computation complexity. Nevertheless, recent studies show that physical attacks, such as fault analysis and side-channel analysis, on hardware platform can reveal the cipher key with limited fault-free and faulty ciphertexts. These lightweight and low-cost physical attacks bring a huge challenge on embedded devices. Thus, investigation and analysis of modern embedded devices under physical attacks become a critical procedure to build a robust and reliable Internet of Things (IoT) network. This project was conducted to examine various types of physical attack techniques, including Differential Power Analysis (DPA), Correlation Power Analysis (CPA) and Differential Fault Analysis (DFA). ChipWhisperer capture board and python interface was utilized to initiate the attack against AES implemented on XMEGA microcontroller and CW305 FPGA board. In the case of targeting AES on XMEGA microcontroller, a DPA attack successfully broke the AES-128 key by collecting 1200 power traces within 2 minutes. On the other hand, a CPA attack only required 50 traces and 11 seconds to reveal the key. Exploiting second-order CPA attack against a fully-masked AES was also conducted. After collecting 500 traces and using 7 minutes 23 seconds, the AES key was successfully broken. Moreover, DFA can reveal the key by injecting one byte of fault twice and performing 2 seconds of analysis on two faulty ciphertexts. If only one fault injection is permitted, DFA still can crack the AES, but with 16 minutes post-processing time. The results of these experiments show that AES algorithm has many security vulnerabilities in terms of physical implementation. It is imperative to design a protection scheme on AES that takes into account all of these possible physical attacks.en_US
dc.language.isoenen_US
dc.publisherNanyang Technological Universityen_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleBreaking the hardware implementation of AES encryptionen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorChang Chip Hongen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineering (Electrical and Electronic Engineering)en_US
dc.contributor.supervisoremailECHChang@ntu.edu.sgen_US
item.grantfulltextrestricted-
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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