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https://hdl.handle.net/10356/149987
Title: | Implementation of asynchronous-logic AES algorithm and simulation of side-channel attacks on Xilinx FPGA platform | Authors: | Lai, Bo Liang | Keywords: | Engineering::Electrical and electronic engineering | Issue Date: | 2021 | Publisher: | Nanyang Technological University | Source: | Lai, B. L. (2021). Implementation of asynchronous-logic AES algorithm and simulation of side-channel attacks on Xilinx FPGA platform. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149987 | Project: | A2077-201 | Abstract: | Encryption is a function that is essential in today’s ever growing technological environment. The Advance Encryption Standard has been the most important and widely used cryptography algorithm in the world ever since it was first endorsed by the National Institutes of Standard and Technology. However, despite its popularity in various industries applications, Side Channel Attack (SCA) can obtain the secret key used during the AES encryption process. SCA came in various forms ranging from electromagnetic to Power Analysis. The Correlation Power Attack, a form of SCA will be conducted in this project to analyze the vulnerability of AES to SCA. This project aims to implement an AES algorithm into the Field Programmable Gate Array (FPGA) Board to form a cryptographic device. | URI: | https://hdl.handle.net/10356/149987 | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
File | Description | Size | Format | |
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FYP_Report_Final_Submission.pdf Restricted Access | Final Year Report | 2.01 MB | Adobe PDF | View/Open |
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