Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/150059
DC FieldValueLanguage
dc.contributor.authorJiang, Yushanen_US
dc.contributor.authorWang, Dongen_US
dc.contributor.authorChan, Pak Kwongen_US
dc.date.accessioned2021-06-04T03:42:34Z-
dc.date.available2021-06-04T03:42:34Z-
dc.date.issued2019-
dc.identifier.citationJiang, Y., Wang, D. & Chan, P. K. (2019). A quiescent 407-nA output-capacitorless low-dropout regulator with 0-100-mA load current range. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 27(5), 1093-1104. https://dx.doi.org/10.1109/TVLSI.2018.2890698en_US
dc.identifier.issn1063-8210en_US
dc.identifier.other0000-0003-0846-9172-
dc.identifier.other0000-0002-8854-9203-
dc.identifier.other0000-0002-9205-0819-
dc.identifier.urihttps://hdl.handle.net/10356/150059-
dc.description.abstractAn ultralow quiescent current output-capacitorless low-dropout (LDO) regulator dedicated to Internet-of-Things applications is presented. This is based on an improved adaptive-stage adaptively biased architecture together with the novel frequency compensation to achieve the good stability and fast transient response under ultralow bias current. Validated by the CMOS 0.18-\mu \text{m} technology, the chip area is 0.055 mm². The proposed LDO regulator consumes only 407-nA quiescent current at no-load current while providing a 1-V output with a maximum load current of 100 mA from a 1.2-V power supply. The adaptive frequency compensation is presented, including a new transistor degeneration frequency compensation (TDFC) to sustain the stability at ultralow quiescent bias. Besides, it also includes Q-reduction and Miller-RC compensation schemes to ensure the stability for full load current range. In addition, a substantial improved transient response is obtained by the proposed distributed overshoot reduction circuit together with the TDFC scheme and the adaptively feed-forward biasing topology. The measured results have shown that the undershoot/overshoot voltage is 117 mV/35.33 mV and the output can settle in 1.56~\mu \text{s} with 1% accuracy. Compared to fixed-biased and adaptively biased architectures, it shows the lowest value in figure of merit (FOM) at the quiescent state. Compared to adaptively biased architectures, it shows the improved FOM at the maximum quiescent state.en_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleA quiescent 407-nA output-capacitorless low-dropout regulator with 0-100-mA load current rangeen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doi10.1109/TVLSI.2018.2890698-
dc.identifier.scopus2-s2.0-85065059449-
dc.identifier.issue5en_US
dc.identifier.volume27en_US
dc.identifier.spage1093en_US
dc.identifier.epage1104en_US
dc.subject.keywordsFrequency Compensationen_US
dc.description.acknowledgementThis work was supported in part by the Silicon Labs and in part by EDB Singapore through the JIP Scholarship.en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
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