Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/150291
Title: 16 bits high speed CMOS multiplier IC design
Authors: Wut Yee Win Thoung
Keywords: Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2021
Publisher: Nanyang Technological University
Source: Wut Yee Win Thoung (2021). 16 bits high speed CMOS multiplier IC design. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/150291
Abstract: High Speed VLSI circuits have become a key criterion for developing energy-efficient electronics for high-performance and portable applications. The multipliers are the most important component in designing an energy-efficient processor, as the multiplier design determines the efficiency. Half adders and complete adders are commonly used in digital multipliers and decreasing the number of adders reduces the multiplier's power dissipation. To execute partial product additions, the Wallace Tree Algorithm and Modified Booth Algorithm have been proposed in this project. For the final addition of partial products, the Ripple Carry Adder has been proposed.
URI: https://hdl.handle.net/10356/150291
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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