16 bits high speed CMOS multiplier IC design

Abstract

High Speed VLSI circuits have become a key criterion for developing energy-efficient electronics for high-performance and portable applications. The multipliers are the most important component in designing an energy-efficient processor, as the multiplier design determines the efficiency. Half adders and complete adders are commonly used in digital multipliers and decreasing the number of adders reduces the multiplier's power dissipation. To execute partial product additions, the Wallace Tree Algorithm and Modified Booth Algorithm have been proposed in this project. For the final addition of partial products, the Ripple Carry Adder has been proposed.