Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/150987
Title: A 34-fps 698-GOP/s/W binarized deep neural network-based natural scene text interpretation accelerator for mobile edge computing
Authors: Li, Yixing
Liu, Zichuan
Liu, Wenye
Jiang, Yu
Wang, Yongliang
Goh, Wang Ling
Yu, Hao
Ren, Fengbo
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Li, Y., Liu, Z., Liu, W., Jiang, Y., Wang, Y., Goh, W. L., Yu, H. & Ren, F. (2018). A 34-fps 698-GOP/s/W binarized deep neural network-based natural scene text interpretation accelerator for mobile edge computing. IEEE Transactions On Industrial Electronics, 66(9), 7407-7416. https://dx.doi.org/10.1109/TIE.2018.2875643
Project: MOE2015-T2-2-013
Journal: IEEE Transactions on Industrial Electronics
Abstract: The scene text interpretation is a critical part of the natural scene interpretation. Currently, most of the existing work is based on high-end graphics processing units (GPUs) implementation, which is commonly used on the server side. However, in Internet of Things (IoT) application scenarios, the communication overhead from the edge device to the server is quite large, which sometimes even dominates the total processing time. Hence, the edge-computing oriented design is needed to solve this problem. In this paper, we present an architectural design and implementation of a natural scene text interpretation (NSTI) accelerator, which can classify and localize the text region on pixel-level efficiently in real-time on mobile devices. To target the real-time and low-latency processing, the binary convolutional encoder-decoder network is adopted as the core architecture to enable massive parallelism due to its binary feature. Massively parallelized computations and a highly pipelined data flow control enhance its latency and throughput performance. In addition, all the binarized intermediate results and parameters are stored on chip to eliminate the power consumption and latency overhead of the off-chip communication. The NSTI accelerator is implemented in a 40 nm CMOS technology, which can process scene text images (size of 128 × 32) at 34 fps and latency of 40 ms for pixelwise interpretation with the pixelwise classification accuracy over 90% on ICDAR-03 and ICDAR-13 dataset. The real energy-efficiency is 698 GOP/s/W and the peak energy-efficiency can get up to 7825 GOP/s/W. The proposed accelerator is 7 times more energy efficient than its optimized GPU-based implementation counterpart, while maintaining a real-time throughput with latency of 40 ms.
URI: https://hdl.handle.net/10356/150987
ISSN: 0278-0046
DOI: 10.1109/TIE.2018.2875643
Rights: © 2018 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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