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|Title:||Design of a radiation-hardened-by-design (RHBD) I²C controller||Authors:||Ng, Wei Yet||Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2021||Publisher:||Nanyang Technological University||Source:||Ng, W. Y. (2021). Design of a radiation-hardened-by-design (RHBD) I²C controller. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/151051||Project:||A2045-201||Abstract:||Present-day and next generation of satellites require sophisticated, yet high reliability integrated circuits (ICs) in terms of hardware reliability and high data integrity, i.e., ultra-low soft error-rates. In low earth orbit satellites, advanced Commercial-Off-The-Shelf (COTS) ICs, whilst increasingly employed, suffer from data integrity due to irradiation effects from heavy-ion particles. Radiation-Hardened-By-Design (RHBD) is an esoteric circuit design technique to mitigate the said irradiation effects without resorting to exotic and largely unavailable fabrication processes. The NTU research team has designed an ultra-low soft error-rate RHBD standard cells library to achieve soft error-free designs without high overheads, in terms of delay, area, and power. The primary objective of this final year project is to design an RHBD I²C Controller for low earth orbit satellites based on a 65nm CMOS fabrication process. To the best of the author’s knowledge, this is the first-ever attempt for the design of the RHBD I²C Controller.This report presents the complete RHBD design flow which includes register transfer level (RTL), behavioral simulations, syntheses, RHBD cell replacements, and a layout implementation. During the stage of cell replacement, only important cells and signals such as flip-flops and global outputs are radiation-hardened by adding filter circuits and replacing them with the RHBD cells. To verify the aforesaid and evaluate the NTU RHBD cells library, the design is simulated and compared against the non-RHBD design. The I²C controller was designed from scratch using Verilog. It includes an Advanced High-Performance Bus (AHB) to Wishbone bridge, a single master to multi-slave Wishbone interconnect, an I²C master controller, and an I²C slave. The I²C controller was integrated into a 50MHz, 32-bit ARM cortex-M0 microprocessor and 16KB static random-access memory (SRAM) IP. By this means, the user can control the I²C operation using the created C programming functions. It can support 8-bit I²C read, write, repeated start operations, multi-slave communications, and clock stretching. The design was completed from RTL to layout implementation. With the adoption of the NTU ultra-low error RHBD standard cells library,the design is radiation-hardened with a trade-off overheads of 1.14 times delay, 2.21 times area, and 2.92 times power compared its non-RHBD counterpart. In summary, the objectives of this final year project are successfully completed with very good results where the overheads compared to the non-RHBD counterpart is relatively modest. It also demonstrates that COTS ICs, with some modifications, can be rendered radiation hardened without overly excessive overheads.||URI:||https://hdl.handle.net/10356/151051||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
Updated on Sep 27, 2021
Updated on Sep 27, 2021
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