Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/151178
Title: Growth and fabrication of carbon-based three-dimensional heterostructure in through-silicon vias (TSVs) for 3D interconnects
Authors: Zhu, Ye
Tan, Chong Wei
Chua, Shen Lin
Lim, Yu Dian
Tay, Beng Kang
Tan, Chuan Seng
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Zhu, Y., Tan, C. W., Chua, S. L., Lim, Y. D., Tay, B. K. & Tan, C. S. (2018). Growth and fabrication of carbon-based three-dimensional heterostructure in through-silicon vias (TSVs) for 3D interconnects. 2017 19th Electronics Packaging Technology Conference (EPTC), 1-5. https://dx.doi.org/10.1109/EPTC.2017.8277558
Project: MOE2014- T2-2-105 (ARC22/15)
Abstract: Carbon nanomaterials such as graphene and carbon nanotubes (CNTs) have recently received much attention as potential materials proposed for integration in the future semiconductor technologies because of the advantageous properties particularly in thermal and electrical conductivities. Among them, three-dimensional (3D) pillared CNT-graphene nanostructures are especially attractive due to the desirable out-of-plane and in-plane properties. In this work, a growth and fabrication process flow of CNT-graphene heterostructure as filler of TSV for 3D interconnects was designed and explored. First, experiments for the fabrication of top wafer with unfilled TSV of various diameters (5-50μm) and bottom wafer with patterned graphene electrodes and catalyst deposition were completed successfully. Next, top TSV wafer and bottom graphene wafer were bonded and manually ground followed by wet and dry etching to completely remove the handling wafer and buried oxide, exposing the underlying TSV. CNT growth was conducted for both within TSV and free standing on the graphene. Compared to the free-standing growth with sufficient length (~334μm) and high density (~10 11 cm -2 estimated), few via holes have CNTs grown and none was completely filled by CNTs. The inhibited growth of CNTs within unfilled TSV can possibly be attributed to several process-engineering steps involved in wafer-bonding, grinding and wet/dry etching. Further modification and optimization of the process steps need to be done in order to attain higher CNT fillings within the unfilled TSV.
URI: https://hdl.handle.net/10356/151178
ISBN: 9781538630426
DOI: 10.1109/EPTC.2017.8277558
Rights: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/EPTC.2017.8277558.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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