Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/151198
Title: Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation
Authors: Chong, Kwen-Siong
Ng, Jun-Sheng
Chen, Juncheng
Lwin, Ne Kyaw Zwa
Kyaw, Nay Aung
Ho, Weng-Geng
Chang, Joseph
Gwee, Bah-Hwee
Keywords: Engineering::Computer science and engineering::Hardware
Issue Date: 2021
Source: Chong, K., Ng, J., Chen, J., Lwin, N. K. Z., Kyaw, N. A., Ho, W., Chang, J. & Gwee, B. (2021). Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation. IEEE Journal On Emerging and Selected Topics in Circuits and Systems, 11(2), 343-356. https://dx.doi.org/10.1109/JETCAS.2021.3077887
Project: NRF2018NCR-NCR002- 001
NGF-2017-03-013
Journal: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Abstract: We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delay line control and a data-propagation control to amplify the dual-hiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronous logic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs.
URI: https://hdl.handle.net/10356/151198
ISSN: 2156-3365
DOI: 10.1109/JETCAS.2021.3077887
Rights: © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/JETCAS.2021.3077887
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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