Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/151198
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dc.contributor.authorChong, Kwen-Siongen_US
dc.contributor.authorNg, Jun-Shengen_US
dc.contributor.authorChen, Junchengen_US
dc.contributor.authorLwin, Ne Kyaw Zwaen_US
dc.contributor.authorKyaw, Nay Aungen_US
dc.contributor.authorHo, Weng-Gengen_US
dc.contributor.authorChang, Josephen_US
dc.contributor.authorGwee, Bah-Hweeen_US
dc.date.accessioned2021-06-15T01:34:27Z-
dc.date.available2021-06-15T01:34:27Z-
dc.date.issued2021-
dc.identifier.citationChong, K., Ng, J., Chen, J., Lwin, N. K. Z., Kyaw, N. A., Ho, W., Chang, J. & Gwee, B. (2021). Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation. IEEE Journal On Emerging and Selected Topics in Circuits and Systems, 11(2), 343-356. https://dx.doi.org/10.1109/JETCAS.2021.3077887en_US
dc.identifier.issn2156-3365en_US
dc.identifier.urihttps://hdl.handle.net/10356/151198-
dc.description.abstractWe present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delay line control and a data-propagation control to amplify the dual-hiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronous logic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs.en_US
dc.description.sponsorshipNational Research Foundation (NRF)en_US
dc.language.isoenen_US
dc.relationNRF2018NCR-NCR002- 001en_US
dc.relationNGF-2017-03-013en_US
dc.relation.ispartofIEEE Journal on Emerging and Selected Topics in Circuits and Systemsen_US
dc.rights© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/JETCAS.2021.3077887en_US
dc.subjectEngineering::Computer science and engineering::Hardwareen_US
dc.titleDual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluationen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
dc.identifier.doi10.1109/JETCAS.2021.3077887-
dc.description.versionAccepted versionen_US
dc.identifier.issue2en_US
dc.identifier.volume11en_US
dc.identifier.spage343en_US
dc.identifier.epage356en_US
dc.subject.keywordsAdvanced Encryption Standard (AES)en_US
dc.subject.keywordsAsynchronous Circuitsen_US
dc.description.acknowledgementThis research project is supported by the National Research Foundation, Singapore under its National Cybersecurity R&D (NCR) Research Programme in Assuring Hardware Security by Design in Systems on Chip, SOCure (NRF2018NCR-NCR002- 001), and NTUtive GAP fund (NGF-2017-03-013).en_US
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