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https://hdl.handle.net/10356/151198
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DC Field | Value | Language |
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dc.contributor.author | Chong, Kwen-Siong | en_US |
dc.contributor.author | Ng, Jun-Sheng | en_US |
dc.contributor.author | Chen, Juncheng | en_US |
dc.contributor.author | Lwin, Ne Kyaw Zwa | en_US |
dc.contributor.author | Kyaw, Nay Aung | en_US |
dc.contributor.author | Ho, Weng-Geng | en_US |
dc.contributor.author | Chang, Joseph | en_US |
dc.contributor.author | Gwee, Bah-Hwee | en_US |
dc.date.accessioned | 2021-06-15T01:34:27Z | - |
dc.date.available | 2021-06-15T01:34:27Z | - |
dc.date.issued | 2021 | - |
dc.identifier.citation | Chong, K., Ng, J., Chen, J., Lwin, N. K. Z., Kyaw, N. A., Ho, W., Chang, J. & Gwee, B. (2021). Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation. IEEE Journal On Emerging and Selected Topics in Circuits and Systems, 11(2), 343-356. https://dx.doi.org/10.1109/JETCAS.2021.3077887 | en_US |
dc.identifier.issn | 2156-3365 | en_US |
dc.identifier.uri | https://hdl.handle.net/10356/151198 | - |
dc.description.abstract | We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delay line control and a data-propagation control to amplify the dual-hiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronous logic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs. | en_US |
dc.description.sponsorship | National Research Foundation (NRF) | en_US |
dc.language.iso | en | en_US |
dc.relation | NRF2018NCR-NCR002- 001 | en_US |
dc.relation | NGF-2017-03-013 | en_US |
dc.relation.ispartof | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | en_US |
dc.rights | © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/JETCAS.2021.3077887 | en_US |
dc.subject | Engineering::Computer science and engineering::Hardware | en_US |
dc.title | Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation | en_US |
dc.type | Journal Article | en |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.contributor.research | Centre for Integrated Circuits and Systems | en_US |
dc.identifier.doi | 10.1109/JETCAS.2021.3077887 | - |
dc.description.version | Accepted version | en_US |
dc.identifier.issue | 2 | en_US |
dc.identifier.volume | 11 | en_US |
dc.identifier.spage | 343 | en_US |
dc.identifier.epage | 356 | en_US |
dc.subject.keywords | Advanced Encryption Standard (AES) | en_US |
dc.subject.keywords | Asynchronous Circuits | en_US |
dc.description.acknowledgement | This research project is supported by the National Research Foundation, Singapore under its National Cybersecurity R&D (NCR) Research Programme in Assuring Hardware Security by Design in Systems on Chip, SOCure (NRF2018NCR-NCR002- 001), and NTUtive GAP fund (NGF-2017-03-013). | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | EEE Journal Articles |
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File | Description | Size | Format | |
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Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES - Design, Countermeasures and Evaluation.pdf | 12.22 MB | Adobe PDF | View/Open |
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