Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/151445
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dc.contributor.authorBalasubramanian, Padmanabhanen_US
dc.contributor.authorMastorakis, Nikos E.en_US
dc.date.accessioned2021-06-16T02:52:03Z-
dc.date.available2021-06-16T02:52:03Z-
dc.date.issued2021-
dc.identifier.citationBalasubramanian, P. & Mastorakis, N. E. (2021). Area, power and speed optimized early output majority voter for asynchronous TMR implementation. Electronics, 10(12), 1425:1-1425:12. https://dx.doi.org/10.3390/electronics10121425en_US
dc.identifier.issn2079-9292en_US
dc.identifier.urihttps://hdl.handle.net/10356/151445-
dc.description.abstractThis paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero and return-to-one handshake schemes were separately used for data communication. The proposed majority voter requires 62.8% less area and dissipates 37% less power on average compared to the best of the existing asynchronous majority voters while considering both handshake schemes. Importantly, the reductions in area and power are achieved without sacrificing the speed. Example TMR implementations show that the proposed majority voter leads to simultaneous reductions in cycle time, silicon area, and power dissipation. As a result, the proposed majority voter enables improved optimization in figure-of-merits such as area–cycle time product, power–cycle time product, and area–cycle time–power product for TMR implementations utilizing it compared to TMR implementations incorporating other majority voters. The circuits were implemented using a 32/28-nm CMOS technology.en_US
dc.language.isoenen_US
dc.relation.ispartofElectronicsen_US
dc.rights© 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/ 4.0/).en_US
dc.subjectEngineering::Computer science and engineeringen_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleArea, power and speed optimized early output majority voter for asynchronous TMR implementationen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.identifier.doi10.3390/electronics10121425-
dc.description.versionPublished versionen_US
dc.identifier.issue12en_US
dc.identifier.volume10en_US
dc.identifier.spage1425:1en_US
dc.identifier.epage1425:12en_US
dc.subject.keywordsDigital Circuitsen_US
dc.subject.keywordsFault Toleranceen_US
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