Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/152100
Title: A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
Authors: Chacón, Oscar Morales
Wikner, Jacob
Alvandpour, Atila
Siek, Liter
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2020
Source: Chacón, O. M., Wikner, J., Alvandpour, A. & Siek, L. (2020). A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS. 2020 IEEE Nordic Circuits and Systems Conference (NorCAS). https://dx.doi.org/10.1109/NorCAS51424.2020.9265003
Abstract: Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220 mW for 58.6-pJ energy consumption per sample.
URI: https://hdl.handle.net/10356/152100
ISBN: 978-1-7281-9227-7
DOI: 10.1109/NorCAS51424.2020.9265003
Rights: © 2020 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

SCOPUSTM   
Citations 50

1
Updated on Nov 12, 2022

Page view(s)

191
Updated on Nov 25, 2022

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.