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|Title:||Deep neural network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting||Authors:||Lau, Wendy Wee Yee
Ho, Heng Wah
|Keywords:||Engineering::Electrical and electronic engineering::Electric power||Issue Date:||2020||Source:||Lau, W. W. Y., Ho, H. W. & Siek, L. (2020). Deep neural network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting. IEEE Transactions On Circuits and Systems I: Regular Papers, 67(12), 4322-4333. https://dx.doi.org/10.1109/TCSI.2020.3022280||Journal:||IEEE Transactions on Circuits and Systems I: Regular Papers||Abstract:||This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the reverse leakage current. An automated design optimization methodology using Deep Neural Network (DNN) to maximize efficiency is presented. The DNN is shown to accurately model SPICE simulated response of rectifier. Hence, the design phase turnaround time is minimized with fast prediction of optimized design parameters. The proposed rectifier has been fabricated in 65 nm standard CMOS technology. A maximum power conversion efficiency of 73.6% is measured at 2.45 GHz with input power of -6 dBm. The proposed rectifier has a measured sensitivity of -12 dBm for 1 V output voltage.||URI:||https://hdl.handle.net/10356/152104||ISSN:||1549-8328||DOI:||10.1109/TCSI.2020.3022280||Rights:||© 2020 IEEE. All rights reserved.||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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