Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/152105
Title: A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS
Authors: Palaniappan, Arjun Ramaswami
Siek, Liter
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Source: Palaniappan, A. R. & Siek, L. (2019). A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). https://dx.doi.org/10.1109/ISCAS.2019.8702624
Abstract: A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. The TDC core occupies an area of 1.225 mm 2 including the on-chip calibration unit in 180 nm CMOS.
URI: https://hdl.handle.net/10356/152105
ISBN: 978-1-7281-0397-6
ISSN: 2158-1525
DOI: 10.1109/ISCAS.2019.8702624
Rights: © 2019 Institute of Electrical and Electronics Engineers (IEEE). All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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