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Title: A dual redundancy radiation-hardened flip-flop based on C-element in 65nm process
Authors: Jaya, Gibran Limi
Chen, Shoushun
Siek, Liter
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2017
Source: Jaya, G. L., Chen, S. & Siek, L. (2017). A dual redundancy radiation-hardened flip-flop based on C-element in 65nm process. 2016 International Symposium on Integrated Circuits (ISIC), 1-4.
Project: NRF2014SAS-SRP001- 057(2)
Abstract: We propose a radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. We take advantage of the property of C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the Flip-Flop. The Flip-Flop was implemented using 48 transistors and occupied an area of 30.78 um2, using 65nm CMOS process. It consumed 22.6% less transistors as compared to the traditional SEU resilient TMR Flip-flop.
ISBN: 9781467390194
DOI: 10.1109/ISICIR.2016.7829721
Rights: © 2016 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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