Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/152172
Title: A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
Authors: Kong, Junjie
Henzler, Stephan
Schmitt-Landsiedel, Doris
Siek, Liter
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2016
Source: Kong, J., Henzler, S., Schmitt-Landsiedel, D. & Siek, L. (2016). A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 348-351. https://dx.doi.org/10.1109/APCCAS.2016.7803972
Abstract: This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.
URI: https://hdl.handle.net/10356/152172
ISBN: 9781509015702
DOI: 10.1109/APCCAS.2016.7803972
Rights: © 2016 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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