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Title: A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
Authors: Leow, Yoon Hwee
Tang, Howard
Sun, Zhuochao
Siek, Liter
Keywords: Engineering::Computer science and engineering
Issue Date: 2016
Source: Leow, Y. H., Tang, H., Sun, Z. & Siek, L. (2016). A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 51(11), 2625-2638.
Journal: IEEE Journal of Solid-State Circuits 
Abstract: As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and power consumption. To optimize the maximum stable amplitude (MSA) to accommodate a larger input dynamic range, the supply rails have to be expanded, which limited technology choices to those of a larger feature size. This work proposes a 25 kHz 3rd-order continuous-time ΔΣ modulator (CTΔΣM) utilizing a 5-bit SAR quantizer, enabling noise coupling (NC) to be possible in a typical nanoscale CMOS 65 nm technology with VDD of 1 V. Mismatches in SAR comparator and DAC array are mitigated with a proposed calibration scheme while CM mismatches are solved by a floating differential charge storage capacitor (FDCSC) coupling method. To allow sufficient time for SAR bit cycling and noise charge feedback settling, 1 Ts excess loop delay (ELD) is compensated with digital differentiation that minimizes both the power and complexity of the auxiliary feedback DAC. The prototype obtained DR/SNR/SNDR of 103.1 dB/100.1 dB/95.2 dB while dissipating 0.8 mW, hence achieving a FoMSNDR and FoMschreier of 0.34 pJ/level and 177.9 dB, respectively.
ISSN: 0018-9200
DOI: 10.1109/JSSC.2016.2593777
Rights: © 2016 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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