Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/152320
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dc.contributor.authorLi Kanen_US
dc.contributor.authorZheng, Yuanjinen_US
dc.contributor.authorSiek, Literen_US
dc.date.accessioned2021-08-05T05:54:25Z-
dc.date.available2021-08-05T05:54:25Z-
dc.date.issued2017-
dc.identifier.citationLi Kan, Zheng, Y. & Siek, L. (2017). A transient-enhanced low dropout regulator with rail to rail dynamic impedance attenuation buffer suitable for commercial design. Microelectronics Journal, 63, 27-34. https://dx.doi.org/10.1016/j.mejo.2017.02.017en_US
dc.identifier.issn0026-2692en_US
dc.identifier.urihttps://hdl.handle.net/10356/152320-
dc.description.abstractA low-dropout regulator (LDO) for portable application with a high output swing and dynamic biased impedance-attenuation buffer is presented in this paper. The proposed buffer pushes the dominated pole introduced by the LDO's power FET to higher frequency without consuming large quiescent current. The LDO loop with only one dominant pole within unity gain loop bandwidth is realized. A dynamic current sensing circuit is adopted to make the design more robust. The buffer features a rail-to-rail swing which makes the LDO's power FET size smaller than traditional buffer design for the same current deliverability. A low cost method for trimming is introduced to achieve high yield suitable for commercial design. The LDO has been fabricated in a 0.18 µm HV CMOS process. It draws a total current of 40 µA and is able to deliver up to 600 mA of load current. The proposed method for trimming allows for a high yield of approaching 100%, with line/load regulation error <2%, and the maximum transient output voltage variation of 3% with a load step from 1 mA to 600 mA in 100 ns.en_US
dc.language.isoenen_US
dc.relation.ispartofMicroelectronics Journalen_US
dc.rights© 2017 Elsevier Ltd. All rights reserved.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleA transient-enhanced low dropout regulator with rail to rail dynamic impedance attenuation buffer suitable for commercial designen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.researchVIRTUS, IC Design Centre of Excellenceen_US
dc.identifier.doi10.1016/j.mejo.2017.02.017-
dc.identifier.volume63en_US
dc.identifier.spage27en_US
dc.identifier.epage34en_US
dc.subject.keywordsLinear Regulatoren_US
dc.subject.keywordsHigh Output Swing Bufferen_US
dc.subject.keywordsPower FETen_US
dc.subject.keywordsLoop Stabilityen_US
dc.subject.keywordsOffset Trimen_US
item.fulltextNo Fulltext-
item.grantfulltextnone-
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