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|Title:||Development of resistive random access memory for next-generation embedded non-volatile memory application||Authors:||Sun, Jianxun||Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2020||Publisher:||Nanyang Technological University||Source:||Sun, J. (2020). Development of resistive random access memory for next-generation embedded non-volatile memory application. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/152482||Project:||RCA-16/335
|Abstract:||Resistive random access memory (RRAM) is a promising candidate for the next-generation non-volatile memory owing to its simple structure, fast read/write speed, low power consumption, high memory density, and complementary metal oxide semiconductor (CMOS) compatibility. However, many challenges such as high forming voltage, switching variation, thermal stability, and reliability degradation have hindered the high volume production of RRAM devices. In this work, engineering approaches from different perspectives have been implemented to improve the performance of the RRAM devices. To have a better picture of the work done, two terms “macro” and “micro” are introduced. The term “macro” refers to the work carried out at the device operation level such as forming, set, and reset, while the term “micro” refers to the work conducted at the device fabrication level like structural modification and interfacial engineering. Prior works have been accomplished at the “macro” level to achieve multi-level cell (MLC) operation. It is well known that the MLC can be obtained through tuning of the DC operation parameters like set compliance current (CC) and reset stop voltage (SV). Since the larger the resistance window, the more levels could be accommodated, it is important to know the boundaries of the DC parameters. However, the method of finding the boundaries has not been documented. In this thesis, the progressive analysis of the resistive switching I-V characteristics has been adopted to explore the upper and lower bounds of the DC parameters. The significant changes of the I-V curves have been observed when the DC parameters are out of the ranges. It is also found that the conventional way of doing MLC operation by varying one parameter while fixing the other one would lead to the drifting of resistances. Hence, the concept of dynamic boundaries has been proposed after taking the evolution of the filament into account. Experimental results show that the drifting has been mitigated by slightly reducing the reset SV. As the forming voltage of the RRAM devices is usually higher than the operation voltages, it becomes a hurdle for the low voltage CMOS circuits. Pulse engineering (“macro” level) is a known method to reduce the forming voltage. Unfortunately, the demonstrated reduction percentage is only 10%. It is found that the voltage amplitude of the noise signal which triggers the forming process is much lower than the unipolar pulse height. Since the noise signal is generated by switching the halogen lamp, the light factor has been investigated. Based on the results of the “dark test”, it is highly speculated that the reduction of the forming voltage is attributed to the facilitation effect of the negative voltage. A novel bipolar pulse writing scheme is proposed to verify the above hypothesis. Experimental results show that the reduction percentage of the forming voltage is more than 30%, which is much higher than the reported value. Besides, the variability of the forming voltage also gets improved by more than 50%. On the contrary, the inhibition effect of the negative voltage is observed for the set process, which implies that the role of the negative voltage varies with the state of the device. The resistive switching variability and reliability degradation are the two major roadblocks for the development of RRAM devices. Electrode structure engineering (“micro” level) is known to be effective for the improvement of the above two performance metrics. Nonetheless, instead of two electrodes, only one of the electrodes is structurally modified based on the prior works. Here, to attain better filaments confinement, both electrodes of the RRAM devices are engineered. The unique geometric parameters such as electrode angle (EA), electrode spacing (ES), and electrode trench depth (ETD) associated with the double wedge-like electrodes are examined. Apart from the resistive switching uniformity, the reliability performance is significantly improved for the device with small EA, narrow ES, and deep ETD owing to the electric field confinement and enhancement. The thermal budget of the standard integrated circuits (IC) manufacturing process is one of the key considerations even in the design stage of the RRAM devices. Nevertheless, such an important criterion seems to be overlooked by many of the research works. The duration of the thermal stability test reported has been less than or equal to one hour, which is not sufficient for the modern IC fabrication process. In this study, the thermal budget test is carried out by subjecting the RRAM devices to post-metalization annealing (PMA) at 400°C for more than 3 hrs. With the proper engineering of the oxidation reaction at the top metal/metal oxide interface (“micro” level), a device with the sandwich-like (TiN/Ti/TiN) top electrode exhibits better performance in thermal stability, forming, switching uniformity, and endurance when compared to other devices with a single layer (TiN) or bi-layer (TiN/Ti) top electrode. It is common knowledge that noble metals such as Pt, Au, Ir, and Ru are quite costly and hard to etch for the semiconductor industry. Despite that, these materials are widely used to form the electrodes of RRAM devices due to the chemical inertness. Good resistive switching has been demonstrated for the device with Pt bottom electrode (BE) in chapter 6. However, the degradation of switching uniformity is observed when Pt is replaced by TiN, which is a conventional fab material. The oxygen plasma treatment (OPT) has been implemented to passivate the TiN surface before the deposition of switching material. The switching uniformity and resistance window are improved at the expense of increased forming voltage possibly due to the reduction of defects at the bottom metal/metal oxide interface (“micro” level). RRAM cells with moderate OPT have been successfully integrated with thin film transistors (TFT) at the mini array level to demonstrate the possibility of practical application in the field of large-area electronics (LAE).||URI:||https://hdl.handle.net/10356/152482||DOI:||10.32657/10356/152482||Schools:||School of Electrical and Electronic Engineering||Organisations:||Globalfoundries||Rights:||This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Sep 29, 2023
Updated on Sep 29, 2023
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