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Title: A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
Authors: Jo, Yong-Jun
Kim, Ju Eon
Baek, Kwang-Hyun
Kim, Tony Tae-Hyoung
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2021
Source: Jo, Y., Kim, J. E., Baek, K. & Kim, T. T. (2021). A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS. IEEE Transactions On Circuits and Systems II: Express Briefs, 68(9), 3088-3092.
Journal: IEEE Transactions on Circuits and Systems II: Express Briefs
Abstract: A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step.
ISSN: 1549-7747
DOI: 10.1109/TCSII.2021.3097126
Rights: © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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