Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/153402
Title: Gate-level static approximate adders : a comparative analysis
Authors: Balasubramanian, Padmanabhan
Nayar, Raunaq
Maskell, Douglas Leslie
Keywords: Engineering::Computer science and engineering
Engineering::Electrical and electronic engineering
Issue Date: 2021
Source: Balasubramanian, P., Nayar, R. & Maskell, D. L. (2021). Gate-level static approximate adders : a comparative analysis. Electronics, 10(23), 2917-. https://dx.doi.org/10.3390/electronics10232917
Project: MOE2018-T2-2-024
Journal: Electronics
Abstract: Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable.
URI: https://hdl.handle.net/10356/153402
ISSN: 2079-9292
DOI: 10.3390/electronics10232917
Rights: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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