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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Zhang, Jianyu | en_US |
dc.date.accessioned | 2021-12-20T02:37:48Z | - |
dc.date.available | 2021-12-20T02:37:48Z | - |
dc.date.issued | 2021 | - |
dc.identifier.citation | Zhang, J. (2021). Design of a power supply rejection enhancer for analog circuits dedicated to mixed-signal environment. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/154245 | en_US |
dc.identifier.uri | https://hdl.handle.net/10356/154245 | - |
dc.description.abstract | A new power supply rejection (PSR) based enhancer with small and stable dropout voltage is presented in this work. It is implemented using TSMC-40nm process technology and powered by 1.2V supply voltage. A number of circuit techniques are proposed in this work. These include the temperature compensation of Level-Shifted Flipped Voltage Follower (LSFVF), Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and dropout voltage of the enhancer is 1.1127V and 87.3mV, respectively. The Monte-Carlo simulation of this output voltage yields a mean T.C. of 29.4ppm/℃ from -20℃ and 80℃. Besides, the dropout voltage has been verified with good immunity against Process, Temperature and Process (PVT) variation through the worst-case simulation. Consuming only 4.75μA, the circuit can drive load up to 500μA to yield additional PSR improvement of 36dB and 20dB of PSR at 1 Hz and 1MHz, respectively for the analog circuit of interest. This is demonstrated through the application of enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge sensor signal. The comparative Monte-Carlo simulation results on respective DDA circuit have revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction with respect to that of the conventional counterpart over the operation temperature range in typical operation condition. Due to simplicity without voltage reference and operational amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is very useful for supply noise sensitive analog circuits in mixed-signal applications. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Nanyang Technological University | en_US |
dc.relation | ISM-DISS-02224 | en_US |
dc.subject | Engineering::Electrical and electronic engineering::Integrated circuits | en_US |
dc.title | Design of a power supply rejection enhancer for analog circuits dedicated to mixed-signal environment | en_US |
dc.type | Thesis-Master by Coursework | en_US |
dc.contributor.supervisor | Chan Pak Kwong | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Master of Science (Electronics) | en_US |
dc.contributor.supervisoremail | epkchan@ntu.edu.sg | en_US |
item.grantfulltext | restricted | - |
item.fulltext | With Fulltext | - |
Appears in Collections: | EEE Theses |
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File | Description | Size | Format | |
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Amended dissertation_ZHANGJIANYU.pdf Restricted Access | 3.91 MB | Adobe PDF | View/Open |
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