Power- and area-efficient analog-to-digital conversion for in-memory computing

Abstract

In-Memory Computation has received a lot of attention in recent years as a method to solve the von Neumann bottleneck. In CIM operations, ADCs are often needed to convert the analog voltage to obtain digital codes. However, today's ADCs for CIM often require a large amount of silicon area in the structure and operating power consumption. Therefore, ADCs used in CIM structures often have high requirements for power consumption and silicon area. In this paper, a monotonic switching SAR ADC is implemented and some improvements are made to its comparator and control logic to reduce the power consumption and silicon area. The metal-insulator-metal structure is also used to reduce the parasitic capacitance at the top plate of the DAC capacitor array to reduce the gain error. Using 65-nm technology for simulation, the ENOB is 9.64 bits, SNR is 59.94 dB, SNDR is 59.81 dB, SFDR is 73.51 dB, power consumption is 18.7 μW, and FOM is 2.34 fJ/Conv.-step at a supply voltage of 0.8V and a sampling rate of 10 MS/s.