Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/154460
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dc.contributor.authorHu, Jingweien_US
dc.contributor.authorBaldi, Marcoen_US
dc.contributor.authorSantini, Paoloen_US
dc.contributor.authorZeng, Nengen_US
dc.contributor.authorLing, Sanen_US
dc.contributor.authorWang, Huaxiongen_US
dc.date.accessioned2021-12-23T01:39:36Z-
dc.date.available2021-12-23T01:39:36Z-
dc.date.issued2020-
dc.identifier.citationHu, J., Baldi, M., Santini, P., Zeng, N., Ling, S. & Wang, H. (2020). Lightweight key encapsulation using LDPC codes on FPGAs. IEEE Transactions On Computers, 69(3), 327-341. https://dx.doi.org/10.1109/TC.2019.2948323en_US
dc.identifier.issn0018-9340en_US
dc.identifier.urihttps://hdl.handle.net/10356/154460-
dc.description.abstractIn this paper, we present a lightweight hardware design for a recently proposed quantum-safe key encapsulation mechanism based on QC-LDPC codes called LEDAkem, which has been admitted as a round-2 candidate to the NIST post-quantum standardization project. Existing implementations focus on high speed while few of them take into account area or power efficiency, which are particularly decisive for low-cost or power constrained IoT applications. The solution we propose aims at maximizing the metric of area efficiency by rotating the QC-LDPC code representations amongst the block RAMs in digit level. Moreover, optimized parallelized computing techniques, lazy accumulation and block partition are exploited to improve key decapsulation in terms of area and timing efficiency. We show for instance that our area-optimized implementation for 128-bit security requires 6.82× 1056.82×105 cycles and 2.26× 1062.26×106 cycles to encapsulate and decapsulate a shared secret, respectively. The area-optimized design uses only 39 slices (3 percent of the available logic) and 809 slices (39 percent of the available logic) for key encapsulation and key decapsulation respectively, on a small-size low-end Xilinx Spartan-6 FPGA.en_US
dc.description.sponsorshipMinistry of Education (MOE)en_US
dc.description.sponsorshipNational Research Foundation (NRF)en_US
dc.language.isoenen_US
dc.relationMOE2016-T2-2-014(S)en_US
dc.relation.ispartofIEEE Transactions on Computersen_US
dc.rights© 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.en_US
dc.subjectScience::Mathematicsen_US
dc.titleLightweight key encapsulation using LDPC codes on FPGAsen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Physical and Mathematical Sciencesen_US
dc.contributor.departmentDivision of Mathematical Scienceen_US
dc.identifier.doi10.1109/TC.2019.2948323-
dc.identifier.scopus2-s2.0-85079648808-
dc.identifier.issue3en_US
dc.identifier.volume69en_US
dc.identifier.spage327en_US
dc.identifier.epage341en_US
dc.subject.keywordsPost-Quantum Cryptographyen_US
dc.subject.keywordsKey Encapsulation Mechanismen_US
dc.description.acknowledgementThis work was partially supported by Singapore Ministry of Education under Research Grant MOE2016-T2-2-014(S) and the National Research Foundation, Prime Ministers Office, Singapore under its Strategic Capability Research Centres Funding Initiative.en_US
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