Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/154464
Title: High throughput/gate AES hardware architectures based on datapath compression
Authors: Ueno, Rei
Homma, Naofumi
Morioka, Sumio
Miura, Noriyuki
Matsuda, Kohei
Nagata, Makoto
Bhasin, Shivam
Mathieu, Yves
Graba, Tarik
Danger, Jean-Luc
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Source: Ueno, R., Homma, N., Morioka, S., Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Mathieu, Y., Graba, T. & Danger, J. (2019). High throughput/gate AES hardware architectures based on datapath compression. IEEE Transactions On Computers, 69(4), 534-548. https://dx.doi.org/10.1109/TC.2019.2957355
Journal: IEEE Transactions on Computers 
Abstract: This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.
URI: https://hdl.handle.net/10356/154464
ISSN: 0018-9340
DOI: 10.1109/TC.2019.2957355
Rights: © 2020 The Author(s). This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:NTC Journal Articles

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