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Title: Fault-tolerant routing mechanism in 3D optical network-on-chip based on node reuse
Authors: Guo, Pengxing
Hou, W.
Guo, L.
Sun, W.
Liu, C.
Bao, H.
Duong, Luan H. K.
Liu, Weichen
Keywords: Engineering::Computer science and engineering
Issue Date: 2020
Source: Guo, P., Hou, W., Guo, L., Sun, W., Liu, C., Bao, H., Duong, L. H. K. & Liu, W. (2020). Fault-tolerant routing mechanism in 3D optical network-on-chip based on node reuse. IEEE Transactions On Parallel and Distributed Systems, 31(3), 547-564.
Journal: IEEE Transactions on Parallel and Distributed Systems
Abstract: The three-dimensional Network-on-Chips (3D NoCs) has become a mature multi-core interconnection architecture in recent years. However, the traditional electrical lines have very limited bandwidth and high energy consumption, making the photonic interconnection promising for future 3D Optical NoCs (ONoCs). Since existing solutions cannot well guarantee the fault-tolerant ability of 3D ONoCs, in this paper, we propose a reliable optical router (OR) structure which sacrifices less redundancy to obtain more restore paths. Moreover, by using our fault-tolerant routing algorithm, the restore path can be found inside the disabled OR under the deadlock-free condition, i.e., fault-node reuse. Experimental results show that the proposed approach outperforms the previous related works by maximum 81.1 percent and 33.0 percent on average for throughput performance under different synthetic and real traffic patterns. It can improve the system average optical signal to noise ratio (OSNR) performance by maximum 26.92 percent and 12.57 percent on average, and it can improve the average energy consumption performance by 0.3 percent to 15.2 percent under different topology types/sizes, failure rates, OR structures, and payload packet sizes.
ISSN: 1045-9219
DOI: 10.1109/TPDS.2019.2939240
Rights: © 2019 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Journal Articles

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