A high speed 16-bit CMOS multiplier IC design

Abstract

In this dissertation, we investigate some algorithms and use them to implement a 16-bit CMOS multiplier design. A variety of different adders are constructed from half adders and full adders. Meanwhile, a variety of multi-bit adders are used as the basis of the multiplier structure. All of them are studied and developed using Verilog HDL language. By using related algorithms and the adders built above, we will study the performance of each 16-bit multiplier design. In this dissertation, the Vedic algorithm, Array algorithm, Wallace algorithm, and the modified Booth algorithm are proposed to build the 16-bit multiplication. All functional models of 16-bit multiplier were developed in Verilog HDL language. The simulation using the Verilog Compiler was shown to have a successful multiplication function. And schematic obtained by simulation was synthesized on Design Vision in Global Foundry 65nm technology. The simulation results show that Booth-Wallace multiplier has the least propagation delay, and the delay is decreased by 46% compared to the Array multiplier. Therefore, how to make a trade-off between delay and cell area consumption has always been a development direction worth paying attention to in digital system design.