Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/155020
Title: 16-bit low-power CMOS multiplier IC design
Authors: Wang, Jun
Keywords: Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2021
Publisher: Nanyang Technological University
Source: Wang, J. (2021). 16-bit low-power CMOS multiplier IC design. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/155020
Project: ISM-DISS-02408
Abstract: The multiplier is one of the critical units of the microprocessor. The main design principle for a multiplier is a tradeoff balance among structure, speed and area. With the fast development of VLSI, power consumption becomes more significant and cannot meet the current demand. So, the research of low power circuits has been an important project. In this thesis, the main topic is the research of ASIC design of low power multiplier. In this thesis, there are several low power techniques, which are used for designing low power multipliers. Finally, four kinds of 16-bit multipliers are designed. Two different optimization approaches to multiplication are explored. Booth encoding is to optimize the encoding method of multiplicand and multiplier. However, the Wallace tree is to improve the summation part of partial products. The other three multipliers will compare power, cell area, delay time with CSA, which is the benchmark in this thesis. In conclusion, the optimized Booth encoding Multiplier and Wallace Tree Multiplier were implemented with lower power consumption and shorter delay. For the Booth encoder with 3 to 2 and 4 to 2 compressor, the structure of 3 to 2 further improves the power efficiency since the simple structure and smaller cell area.
URI: https://hdl.handle.net/10356/155020
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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