Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/155209
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dc.contributor.authorZeng, Zhengen_US
dc.contributor.authorZhang, Xinen_US
dc.contributor.authorZhang, Zheen_US
dc.date.accessioned2022-02-15T07:49:47Z-
dc.date.available2022-02-15T07:49:47Z-
dc.date.issued2020-
dc.identifier.citationZeng, Z., Zhang, X. & Zhang, Z. (2020). Imbalance current analysis and its suppression methodology for parallel SiC MOSFETs with aid of a differential mode choke. IEEE Transactions On Industrial Electronics, 67(2), 1508-1519. https://dx.doi.org/10.1109/TIE.2019.2901655en_US
dc.identifier.issn0278-0046en_US
dc.identifier.urihttps://hdl.handle.net/10356/155209-
dc.description.abstractParallel connection of silicon carbide (SiC) MOSFETs is a cost-effective solution for high-capacity power converters. However, transient imbalance current, during turn-on and -off processes, challenges the safety and stability of parallel SiC MOSFETs. In this paper, considering the impact factors of device parameters, circuit parasitics, and junction temperatures, in-depth mathematical models are created to reveal the electrothermal mechanisms of the imbalance current. Moreover, with the incorporation of a differential mode choke (DMC), an effective approach is proposed to suppress the imbalance current among parallel SiC MOSFETs. Physics concepts, operation principles, and design guidelines of the DMC-based suppression method are fully presented. Besides, to reduce the equivalent leakage inductance and equivalent parallel capacitance of the DMC, winding patterns of the DMC are comparatively studied and optimized to suppress turn-off over-voltage and switching ringing. Concerning the influence of winding patterns, load currents, gate resistances, and junction temperatures, experimental results are comprehensively demonstrated to confirm the validity of theoretical models and the function of the proposed DMC-based suppression method. It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on-off trajectories of parallel SiC MOSFETs.en_US
dc.description.sponsorshipMinistry of Education (MOE)en_US
dc.language.isoenen_US
dc.relationRG 85/18en_US
dc.relation.ispartofIEEE Transactions on Industrial Electronicsen_US
dc.rights© 2019 IEEE. All rights reserved.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleImbalance current analysis and its suppression methodology for parallel SiC MOSFETs with aid of a differential mode chokeen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doi10.1109/TIE.2019.2901655-
dc.identifier.scopus2-s2.0-85071610500-
dc.identifier.issue2en_US
dc.identifier.volume67en_US
dc.identifier.spage1508en_US
dc.identifier.epage1519en_US
dc.subject.keywordsParallel SiC MOSFETsen_US
dc.subject.keywordsMechanism of Imbalance Currenten_US
dc.description.acknowledgementThis work was supported in part by the Chinese National Natural Science Foundation under Grant 51607016, in part by the Chinese National Key Research & Development Program under Grant 2017YFB0102 303, and in part by Singapore ACRF Tier 1 under Grant RG 85/18, as well as in part by the start-up grant (SCOPES) of Professor Xin Zhangen_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
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