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|Title:||ADEPOS : a novel approximate computing framework for anomaly detection systems and its implementation in 65-nm CMOS||Authors:||Bose, Sumon Kumar
Gopalakrishnan, Pradeep Kumar
|Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2019||Source:||Bose, S. K., Kar, B., Roy, M., Gopalakrishnan, P. K., Zhang, L., Patil, A. & Basu, A. (2019). ADEPOS : a novel approximate computing framework for anomaly detection systems and its implementation in 65-nm CMOS. IEEE Transactions On Circuits and Systems I: Regular Papers, 67(3), 913-926. https://dx.doi.org/10.1109/TCSI.2019.2958086||Journal:||IEEE Transactions on Circuits and Systems I: Regular Papers||Abstract:||To overcome the energy and bandwidth limitations of traditional IoT systems, 'edge computing' or information extraction at the sensor node has become popular. However, now it is important to create very low energy information extraction or pattern recognition systems. In this paper, we present an approximate computing method to reduce the computation energy of a specific type of IoT system used for anomaly detection (e.g. in predictive maintenance, epileptic seizure detection, etc). Termed as Anomaly Detection Based Power Savings (ADEPOS), our proposed method uses low precision computing and low complexity neural networks at the beginning when it is easy to distinguish healthy data. However, on the detection of anomalies, the complexity of the network and computing precision are adaptively increased for accurate predictions. We show that ensemble approaches are well suited for adaptively changing network size. To validate our proposed scheme, a chip has been fabricated in UMC 65nm process that includes an MSP430 microprocessor along with an on-chip switching mode DC-DC converter for dynamic voltage and frequency scaling. Using NASA bearing dataset for machine health monitoring, we show that using ADEPOS we can achieve 8.95X saving of energy along the lifetime without losing any detection accuracy. The energy savings are obtained by reducing the execution time of the neural network on the microprocessor.||URI:||https://hdl.handle.net/10356/155305||ISSN:||1549-8328||DOI:||10.1109/TCSI.2019.2958086||Rights:||© 2019 IEEE. All rights reserved.||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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