Energy-efficient data-aware SRAM design utilizing column-based data encoding

Abstract

This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of '0s'. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for '0'. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 $\mu \text{W}$ and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V.