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https://hdl.handle.net/10356/155784
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DC Field | Value | Language |
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dc.contributor.author | Luo, Xiangzhong | en_US |
dc.contributor.author | Liu, Di | en_US |
dc.contributor.author | Huai, Shuo | en_US |
dc.contributor.author | Liu, Weichen | en_US |
dc.date.accessioned | 2022-03-22T01:31:04Z | - |
dc.date.available | 2022-03-22T01:31:04Z | - |
dc.date.issued | 2021 | - |
dc.identifier.citation | Luo, X., Liu, D., Huai, S. & Liu, W. (2021). HSCoNAS : hardware-software co-design of efficient DNNs via neural architecture search. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). https://dx.doi.org/10.23919/DATE51398.2021.9473937 | en_US |
dc.identifier.uri | https://hdl.handle.net/10356/155784 | - |
dc.description.abstract | In this paper, we present a novel multi-objective hardware-aware neural architecture search (NAS) framework, namely HSCoNAS, to automate the design of deep neural networks (DNNs) with high accuracy but low latency upon target hardware. To accomplish this goal, we first propose an effective hardware performance modeling method to approximate the runtime latency of DNNs on target hardware, which will be integrated into HSCoNAS to avoid the tedious on-device measurements. Besides, we propose two novel techniques, \textit{i.e.}, dynamic channel scaling to maximize the accuracy under the specified latency and progressive space shrinking to refine the search space towards target hardware as well as alleviate the search overheads. These two techniques jointly work to allow HSCoNAS to perform fine-grained and efficient explorations. Finally, an evolutionary algorithm (EA) is incorporated to conduct the architecture search. Extensive experiments on ImageNet are conducted upon diverse target hardware, \textit{i.e.}, GPU, CPU, and edge device to demonstrate the superiority of HSCoNAS over recent state-of-the-art approaches. | en_US |
dc.description.sponsorship | Ministry of Education (MOE) | en_US |
dc.description.sponsorship | Nanyang Technological University | en_US |
dc.language.iso | en | en_US |
dc.relation | MOE2019-T2-1-071 | en_US |
dc.relation | MOE2019-T1-001-072 | en_US |
dc.relation | M4082282 | en_US |
dc.relation | M4082087 | en_US |
dc.relation.uri | 10.21979/N9/GZJ0PW | en_US |
dc.rights | © 2021 EDAA, published by IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.23919/DATE51398.2021.9473937. | en_US |
dc.subject | Engineering::Computer science and engineering | en_US |
dc.title | HSCoNAS : hardware-software co-design of efficient DNNs via neural architecture search | en_US |
dc.type | Conference Paper | en |
dc.contributor.school | School of Computer Science and Engineering | en_US |
dc.contributor.conference | 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) | en_US |
dc.contributor.research | HP-NTU Digital Manufacturing Corporate Lab | en_US |
dc.identifier.doi | 10.23919/DATE51398.2021.9473937 | - |
dc.description.version | Submitted/Accepted version | en_US |
dc.subject.keywords | Performance Evaluation | en_US |
dc.subject.keywords | Runtime | en_US |
dc.citation.conferencelocation | Grenoble, France | en_US |
dc.description.acknowledgement | This work is partially supported by the Ministry of Education, Singapore, under its Academic Research Fund Tier 2 (MOE2019-T2-1-071) and Tier 1 (MOE2019-T1-001-072), and partially supported by Nanyang Technological University, Singapore, under its NAP (M4082282) and SUG (M4082087). | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | SCSE Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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manuscript.pdf | 1.5 MB | Adobe PDF | View/Open |
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