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Title: UVM testbench development for Quad-SPI controller
Authors: Yu, Zehui
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Yu, Z. (2022). UVM testbench development for Quad-SPI controller. Master's thesis, Nanyang Technological University, Singapore.
Abstract: With the increase in the scale and complexity of Integrated Circuits, the difficulty and workload of verification increase accordingly. Traditional verification methodologies take much time to develop testbenches and testcases. So, improving the efficiency and quality of verification has become a hot topic in the digital integrated circuit verification field. This dissertation uses Universal Verification Methodology with reusable architecture with multiple objects, components, and mechanisms to improve the verification efficiency. The history of verification methodologies as well as the architecture and components of Universal Verification Methodology are reviewed before the verification project. Serial Peripheral Interface is a synchronous serial data transmission protocol, which is applied in more and more integrated circuits because of its simple pin connection. Quad-SPI controller communicates with external Flashes Single/Dual/Quad SPI protocol and handles different functional modes and Flash instructions. The dissertation analyzed and extracted functional points of the Quad-SPI controller. Then a UVM testbench is developed with basic UVM components and Verification Components. Some testcases for main functional modes are also developed based on the UVM testbench. Finally, code and functional coverages are collected with current testcases.
Schools: School of Electrical and Electronic Engineering 
Organisations: Silicon Laboratories International Pte. Ltd. 
Technical University of Munich 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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