Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/156009
Full metadata record
DC FieldValueLanguage
dc.contributor.authorShantanu, Raokeen_US
dc.date.accessioned2022-03-30T12:26:14Z-
dc.date.available2022-03-30T12:26:14Z-
dc.date.issued2022-
dc.identifier.citationShantanu, R. (2022). MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/156009en_US
dc.identifier.urihttps://hdl.handle.net/10356/156009-
dc.description.abstractIoT edge devices of the past were designed primarily of sensors and a microcontroller that controlled the influx of data and the sensor operations. The microcontrollers had some pre-processing capabilities and their subsequent major task was to transmit this data to the central node where all the processing occurred. This hierarchy is not energy efficient as most of power consumed by such a system was spent on data transmission from the edge devices to the parent node in wireless or wired medium. This increased the demand for edge devices with higher computing capabilities so the power envelope of the transmission task is minimal. More computation at the edge also decreases the dependency of the system on fewer or one central node that can stall the system if it faces an error. This work deals with implementing one of the major techniques to reduce the power consumed by an IoT node that is AI capable by integrating non-volatile memory to the L2 memory subsystem of a RISC-V core. This thesis will outline the work done in validating a taped-out chip with on-chip MRAM integrated with the L2 memory of the PULPissimo, followed by the progress done in integrating off-chip MRAM to a vanilla version of PULPissimo.en_US
dc.language.isoenen_US
dc.publisherNanyang Technological Universityen_US
dc.subjectEngineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.subjectEngineering::Electrical and electronic engineering::Microelectronicsen_US
dc.titleMRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applicationsen_US
dc.typeThesis-Master by Courseworken_US
dc.contributor.supervisorKim Tae Hyoungen_US
dc.contributor.supervisorMohamed M. Sabry Alyen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Integrated Circuit Design)en_US
dc.contributor.organizationTechnical University of Munichen_US
dc.contributor.researchHardware & Embedded Systems Lab (HESL)en_US
dc.contributor.supervisoremailTHKIM@ntu.edu.sg, msabry@ntu.edu.sgen_US
item.grantfulltextrestricted-
item.fulltextWith Fulltext-
Appears in Collections:EEE Theses
Files in This Item:
File Description SizeFormat 
MRAM INTEGRATION WITH L2 MEMORY_1.pdf
  Restricted Access
7.26 MBAdobe PDFView/Open

Page view(s)

63
Updated on Jun 25, 2022

Download(s)

4
Updated on Jun 25, 2022

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.