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Title: MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications
Authors: Shantanu, Raoke
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Shantanu, R. (2022). MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications. Master's thesis, Nanyang Technological University, Singapore.
Abstract: IoT edge devices of the past were designed primarily of sensors and a microcontroller that controlled the influx of data and the sensor operations. The microcontrollers had some pre-processing capabilities and their subsequent major task was to transmit this data to the central node where all the processing occurred. This hierarchy is not energy efficient as most of power consumed by such a system was spent on data transmission from the edge devices to the parent node in wireless or wired medium. This increased the demand for edge devices with higher computing capabilities so the power envelope of the transmission task is minimal. More computation at the edge also decreases the dependency of the system on fewer or one central node that can stall the system if it faces an error. This work deals with implementing one of the major techniques to reduce the power consumed by an IoT node that is AI capable by integrating non-volatile memory to the L2 memory subsystem of a RISC-V core. This thesis will outline the work done in validating a taped-out chip with on-chip MRAM integrated with the L2 memory of the PULPissimo, followed by the progress done in integrating off-chip MRAM to a vanilla version of PULPissimo.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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