Radiation hardened RISC-V processor

Abstract

This thesis focuses on designing and validating an open-source 32-bit RISC-V processor and implementing using NTU’s in-house RHBD cell library. We inves tigate, analyse and compare the final layout in timing, area, and power based on three different libraries: (a) Full triple-module-redundancy (TMR) technique using the GF 65nm library (b) DICE library (c) NTU’s in-house library The results show that the RHBD RISC-V design using NTU’s in-house library passes functional tests at 250MHz, and can run higher if a faster SRAM is used. This suggests that NTU’s in-house library is applicable for high-speed applica tions. The results also show that the implementation using our in-house library is about 33% smaller than the implementation using DICE and about 60% smaller than the implementation applying full TMR using the GF 65nm library. In terms of power consumption, the implementation using our in-house library is almost equal to the implementation using the DICE library and 30% smaller than the implementation applying full TMR in the worst case. Overall, in the implementation of the RHBD RISC-V processor, we conclude that the application of NTU’s in-house RHBD library is superior to reported RHBD methodologies, including DICE and TMR.