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Title: Experimental investigation on the performance of ArSMART NoC architecture
Authors: Winson, Marvin
Keywords: Engineering::Computer science and engineering::Hardware::Performance and reliability
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Winson, M. (2022). Experimental investigation on the performance of ArSMART NoC architecture. Final Year Project (FYP), Nanyang Technological University, Singapore.
Project: SCSE21-0168
Abstract: The Network on Chip (NoC) architecture is a communication architecture used as a communication subsystem between various Processing Elements (PEs) in a System-on-Chip (SoC) architecture. The NoC architecture provides promising benefits such as high performance, scalability, redundancy, and relative simplicity by utilizing concepts and techniques commonly found in computer networks. The ArSMART NoC - which is an improvement to the SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) NoC - allows transmission of unconflicted flits over distance PEs in one cycle by establishing a bypass link between each cycle with clockless repeaters. On the SMART NoC, link contention prevents lower priority flits from utilizing the bypass. In order to overcome this, the ArSMART NoC allows arbitrary-turn transmission by delegating the task of route computation to a set of cluster controllers that each manages a subset of the available PEs (in contrast to the cycle-by-cycle table-lookup route arbitration on the SMART NoC). This project simulates the performance of the ArSMART NoC architecture under varying conditions. The number of tasks, in-out degree of nodes, execution time, link latency, and Application Injection Rate degrees are varied. Then the performance of the XY Routing algorithm, the Odd Even routing algorithm, as well as a custom arbitrary turn routing algorithm is simulated and evaluated. The simulation is run on the Gem5 simulator, that has been patched to support the ArSMART NoC architecture and are automated through the use of python scripts. Overall, the algorithm that leverages the arbitrary turn capability provided by ArSMART was able to consistently perform better than both XY and OE routing algorithms throughout 2700 randomly generated task graphs. We were able to reach as high as over 22% latency reduction and 35% contention reduction before plateauing at higher task counts.
Schools: School of Computer Science and Engineering 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Student Reports (FYP/IA/PA/PI)

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