Please use this identifier to cite or link to this item:
Title: SRAM-based in-memory computing for machine learning applications
Authors: Zhao, Yuqin
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Zhao, Y. (2022). SRAM-based in-memory computing for machine learning applications. Master's thesis, Nanyang Technological University, Singapore.
Abstract: In memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In this paper, a 4k weight-selective digital SRAM design is implemented with improvements on Bitcell and Adder Tree. It uses TG logic in the design to improve the speed and eliminate power consumption. The weight-Selective function is used to adapt to the different complexity of the calculation. The simulation is done by using the TSMC65LP process. The Bitcell Array is 64x64, GOPS is 409.6 and the frequency is 200MHz.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
  Restricted Access
3.91 MBAdobe PDFView/Open

Page view(s)

Updated on May 15, 2022


Updated on May 15, 2022

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.