Hardware-software co-design and optimization for point-to-point network-on-chip based many-core systems

Abstract

Many-core systems, which consist of numerous processing elements (PEs), provide high execution parallelism. To connect these PEs, network-on-chip (NoC) is proposed as an efficient on-chip communication paradigm. Nevertheless, NoC faces two challenges in reducing communication overheads. Firstly, the hop-by-hop buffering and arbitration in NoC lead to huge transmission delay and energy consumption. Secondly, NoC resource management strategies, e.g., mapping and routing, are not fully optimized. To address these challenges, we propose software and hardware collaborated methodologies. (1) We propose a software-defined point-to-point NoC architecture, ArSMART, enabling single-cycle multi-hop transmission and application-specific communication optimization. (2) We present a method to co-optimize task mapping and routing to accelerate computation and communication simultaneously, extending ArSMART to heterogeneous systems. (3) We fully utilize the parallelism that exists in NoCs through parallel multipath transmission, further reducing transmission latency in ArSMART. Experiments show our solutions achieve remarkable performance improvement in terms of latency, area, and power.