Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/156847
Title: A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector
Authors: Liang, Yuan
Boon, Chirn Chye
Chen, Qian
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2022
Source: Liang, Y., Boon, C. C. & Chen, Q. (2022). A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector. IEEE Microwave and Wireless Components Letters. https://dx.doi.org/10.1109/LMWC.2022.3153326
Project: MOE2019-T2-1-114
Journal: IEEE Microwave and Wireless Components Letters
Abstract: This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.
URI: https://hdl.handle.net/10356/156847
ISSN: 1531-1309
DOI: 10.1109/LMWC.2022.3153326
Rights: © 2022 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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