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Title: Image classification on a spiking neural network accelerator
Authors: Gao, Wenjia
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Gao, W. (2022). Image classification on a spiking neural network accelerator. Master's thesis, Nanyang Technological University, Singapore.
Project: D-256-20212-03057
Abstract: In the rapid development of artificial intelligence, many data and computing-intensive applications are closely related to our lives. These application scenarios are often characterized by multiple parallelism and repetition, posing a more severe challenge to the pursuit of high-speed and low-power objectives for integrated circuits. However, the traditional bus structure, i.e. the von Neumann structure, which physically separates the computing unit from the storage unit, cannot adapt to these scenarios and has a high power consumption. In order to conquer the von Neumann bottleneck, some models and architectures for in-memory computing (IMC) have been proposed, which embed some logical operations into the memory, reducing the time and power consumption significantly. Static Random-Access Memory (SRAM), as the cache of the central processing unit, has many advantages such as high speed, low power, and good compatibility. The SRAM-based IMC technology integrates the computing unit into the memory and supports the immediate storage and calculation of data and is expected to become a new generation of an intelligent computing architecture for IMC. This dissertation illustrates how to combine IMC with SRAM memory arrays based on a circuit-level macro model, NeuroSim, which simulates parameters such as area, latency, dynamic energy, and leakage power for neural network hardware accelerators. Taking a small handwritten digit dataset MNIST represented by binary file as an example, the image classification is performed by the spiking neural network built in NeuroSim, and an accuracy rate of 70% can be obtained. Subsequently, the designs of 6T SRAM memory cell, row decoder, sense amplifier and master-slave latch pair were carried out based on the 40-nm technology using the UMC40ULP process design kit, where the construction of an overall circuit structure was also accomplished. Simulation results show a linear relationship between the output current and the number of word lines turned on.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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