Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/157280
Title: 32-bit low-delay arithmetic-logic unit
Authors: Mu, Yihao
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Mu, Y. (2022). 32-bit low-delay arithmetic-logic unit. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/157280
Abstract: ALU is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. For example, integer add, substrate, logic and, logic or and shift operation. ALU is also a fundamental component of computing circuits, especially the CPU in computers. The improvement of ALU is an essential topic in modern CPU design history because it is one factor that restricts the frequency of the CPU. A 32-bits high-speed ALU is proposed in this dissertation, and several techniques are combined to improve its performance. CLA is designed to improve the speed of the ALU. Complementary code extends the computational area from natural numbers to integers. A reusable adder is designed to reduce area. Overflow is computed to prevent data error and loss. After using Verilog to build the ALU, the simulation and synthesis are also done with the help of tools such as Design Compiler and Verilog Compiled Simulator, using AMS 0.35um library. The result shows that the 32-bits high-speed ALU leads to 50.4% improvement in delay compared with the benchmarked design.
URI: https://hdl.handle.net/10356/157280
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
32-bit low-delay ALU MuYihao.pdf
  Restricted Access
1.25 MBAdobe PDFView/Open

Page view(s)

36
Updated on Jun 30, 2022

Download(s)

1
Updated on Jun 30, 2022

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.